RSS Feed Source: MIT Technology Review
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Building up: IBM has unveiled a prototype chip that stacks transistors in two vertical layers—a design the company calls a nanostack—doubling the density of its previous state-of-the-art tech and fitting roughly 100 billion transistors onto an area the size of a fingernail.
A meaningful leap in performance: Compared to IBM’s previous state-of-the-art approach, the new design can be used to make chips that handle up to 50% more work in the same amount time and run up to 70% more efficiently—gains that could meaningfully improve energy use in data centers within a decade.
Not without complications: The technology is not yet in production, and stacking transistors introduces real manufacturing headaches: more transistor layers opens up more room for errors, and engineers must build each tier without generating enough heat to melt the connections below—a constraint IBM has solved, though it won’t say how.” data-chronoton-post-id=”1139696″ data-chronoton-expand-collapse=”1″
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